View DS1077Z-120_6637457.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 of 17 042801 features ? processor controlled or standalone solid- state oscillator ? frequency changes on the fly ? dual, low-jitter, synchronous fixed frequency outputs ? 2-wire serial interface ? frequency outputs 8khz - 133mhz ? +/-1% variation over temperature and voltage ? +/-0.5% initial tolerance ? non-volatile frequency settings ? single 5-v supply ? no external components ? power down mode ? synchronous output gating standard frequency option note: x denotes package option ds1077x-133 133.333mhz ? 16.2khz ds1077x-125 125.000mhz ? 15.2khz ds1077x-120 120.000mhz ? 14.6khz ds1077x-100 100.000mhz ? 12.2khz ds1077x-66 66.666mhz ? 8.0khz pin assignments out1 out0 1 2 3 4 vdd gn d sc l ctrl0 ctrl1 sd a 8 7 6 5 pin description out1 main oscillator output out0 reference output v dd power supply voltage gnd ground ctrl1 control pin for out1 ctrl0 control pin for out0 sda 2-wire serial data input/output scl 2-wire serial clock odering information note: xxx denotes frequency option ds1077z-xxx 8 pin 150mil soic ds1077u-xxx 8 pin 118mil usop description the ds1077 is a dual output, programmable, fixed frequency oscillator requiring no external components for operation. the ds1077 can be used as a processor-controlled frequency synthesizer or as a standalone oscillator. the two synchronous output operating frequencies are user adjustable in sub multiples of the matter frequency through the use of two on-chip programmable prescalers and a divider. the specific output frequencies chosen are stored in non-volatile (eeprom) memory. the ds1077 defaults to these values on powerup. the ds1077 features a 2-wire serial interface that allows in-circuit-on-the-fly programming of the programmable prescalers (p0 & p1) and divider (n) with the desired values being stored in non-volatile (eeprom) memory. design changes can be accommodated in-circuit-on-the-fly by simply programming different values into the device (or reprogramming previously programmed devices). alternatively, for fixed frequency applications previously programmed devices can be used and no connection to the serial interface is required. pre-programmed devices can be ordered in customer requested frequencies. the ds1077 is available in 8-pin, soic or usop packages, allowing the generation of a clock signal easily, economically and using minimal board area. chip scale packaging is also available on request. ds1077 econoscillator/divide r www.dalsemi.com preliminary 8-pin & 150 mil soic 118 mil usop package
ds1077 2 of 17 block diagram 1077 figure1 programmable ?n? divider control logic (table 1) control logic two-wire interface div1 0m1 0m0 1m1 1m0 en0 sel0 pdn0 pdn1 control registers scl sda internal oscillator p0 prescaler (m divider) p1 prescaler ( m divider ) 0m0 0m1 1m0 1m1 mux pdn 0 en0 sel0 power down out0 ctrl0 enable select out1 div1 ctrl1 pdn1 (table 2) mclk power down enable
ds1077 3 of 17 overview a block diagram of the ds1077 is shown in figure 1. the ds1077 consists of four major components: internal master oscillator prescalers programmable divider control registers the internal oscillator is factory trimmed to provide a master frequency (master clk) that can be routed directly to the outputs (out0 & out1) or through separate prescalers (p0 & p1). out1 can also be routed through an additional divider (n). the prescaler (p0) divides the master clock by 1,2,4, or 8 to be routed directly to the out0 pin. the prescaler (p1) divides the master clock by 1,2,4, or 8 that can be routed directly to the out1 pin or to the divider (n) input, which is then routed to the out1 pin. the programmable divider (n) divides the prescaler output (p1) by any number selected between 2 and 1025 to provide the main output ( out1) or it can be bypassed altogether by use of the div1 register bit. the value of n is stored in the n register. the control registers are user-programmable through a 2-wire serial interface to determine operating frequency (values of p0, p1 & n) and modes of operation. the register values are stored in eeprom and therefore only need to be programmed to alter frequencies and operating modes. pin descriptions output 1 (out1) this pin is the main oscillator output; its frequency is determined by the control register settings for the prescaler p1 (mode bits 1m1 & 1m0) and divider n (div word). output 0 (out0) a reference output, out0, is taken from the output of the reference select mux. its frequency is determined by the control register settings for ctrl0 and values of prescaler p0 (mode bits 0m1 & 0m0). (refer to table 1) control pin 0 (ctrl0) a multi-functional input pin that can be selected as a mux select, output enable and/or a power down. its function is determined by the user-programmable control register values en0, sel0 and pdn0. (refer to table 1)
ds1077 4 of 17 table 1 en0 (bit) sel0 (bit) pdn0 (bit) ctrl0 (pin) out0 (pin) ctrl0 function device mode 1 hi-z power down 000 0hi-z power * down active 1 master clk/m 010 0master clk mux select active 1hi-z 100 0master clk output enable active 1hi-z 110 0 master clk/m output enable active** 1 hi-z power down x0 1 0master clk power down active 1 hi-z power down x1 1 0 master clk/m power down active *this mode is for applications where out0 is not used, but ctrl0 is used as a device shutdown **default condition control pin 1 (ctrl1) a multi-functional input pin that can be selected as a output enable and/or a power down. its function is determined by the user-programmable control register value of pdn1. (refer to table 2) table 2 pdn1 (bit) ctrl1 (pin) ctrl1 function out 1 device mode 0 0 output enable out clk active ** 0 1 output enable hi-z active ** 1 0 power down out clk active 1 1 power down hi-z power down **default condition note: both ctrl0 and ctrl1 can be configured as power downs, they are internally ?or? connected so that either of the control pins may be used to provide a power down function for the whole device, subject to appropriate settings of the pdn0 and pdn1 register bits. (refer to table 3)
ds1077 5 of 17 table 3 pdn0 (bit) pdn1 (bit) shutdown control 0 0 none* 0 1 ctrl1 1 0 ctrl0 1 1 ctrl0 or ctrl1 *ctrl0 performs a power down if selo and eno are both 0 (see table 1) serial data input/output (sda) input/output pin for the 2-wire serial interface used for data transfer serial clock input (scl) input pin for the 2-wire serial interface used to synchronize data movement on the serial interface. register functions the user-programmable registers can be programmed by the user to determine the mode of operation(mux) , operating frequency (div) and bus settings (bus) . details of how these registers are programmed can be found in a later section; in this section the function of the registers are described. the register setting are non-volatile, the values being stored automatically or as required in eeprom when the registers are programmed via the sda and scl pins. mux word msb lsb msb lsb name * pdn1 pdn0 sel0 en0 0m0 0m1 1m0 1m1 div1 - - - - - - default seeting 0 0 0 1 1 0 0 0 0 0 x x x x x x first data byte second data byte *this bit must be set to ?0? zero div1 (bit) this bit allows the output of the prescaler p1 to be routed directly to the out1 pin (div1=1). the n divider is bypassed so the programmed value of n is ignored. if div1=0 (default) the n divider functions normally. 0m1, 0m0, 1m1, 1m0 (bits) these bits set the prescalers p0 and p1 , to divide by 1, 2, 4, or 8. (refer to table 4) table 4 0m1 0m0 prescaler p0 divisor ?m? 1m1 1m0 prescaler p1 divisor ?m? 00 1 ** 00 1 ** 012012 104104 118118 **default condition
ds1077 6 of 17 en0 (bit) (default en0=1) if en0=1 and pdn0= 0 the ctrl0 pin functions as an output enable for out0, the frequency of the output being determined by the sel0 bit. if pdn0=1, the en0 bit is ignored, ctrl0 will function as a power down, output out0 will always be enabled on power up, its frequency being determined by the sel0 bit. if en0= 0 the function of ctrl0 is determined by the sel0 and pdn0 bits (refer to table 1) sel0 (default sel0=1) if sel0=1 and en0=pdn0=0 the ctrl0 pin determines the state of the mux, (i.e., the output frequency of out0) if ctrl0=0 the output will be the master clock frequency if ctrl0=1 the output will be the output frequency of the m prescaler if either en0 or pdn0 = 1 then sel0 determines the frequency of out0 when it is enabled. if sel0=0 the output will be the master clock frequency if sel0=1 the output will be the output frequency of the m prescaler (refer to table 1) pdn0 (default pdn=0) this bit (if set to 1) causes ctrl0 to perform a power down function, regardless of the setting of the other bits if pdn0=0 the function of ctrl0 is determined by the values of en0 and sel0 note: when en0=sel0=pdn0=0, ctrl0 also functions as a power down. this is a special case where all the out0 circuitry is disabled even when the device is powered up for power to saving when out0 is not used. (refer table 1) pdn1 (default pdn1=0) if pdn1=1, ctrl1 will function as a power down if pdn=0, ctrl1 functions as an output enable for out1 only (refer to table 2) note on output enable and power down: 1. both enables are ?smart? and wait for the output to be low before going to hi-z 2. power down sequence first disables both outputs before powering down the device 3. on power up the outputs are disabled until the clock has stabilized ( ~8000 cycles) 4. in power down mode the device can not be programmed 5. a power down command must persist for at least 2 cycles of the lowest output frequency plus 10 microseconds. div word msb lsb msb lsb n9n8n7n6n5n4n3n2n1n0xxxxxx first data byte second data byte n these ten bits determine the value of the programmable divider (n). the range of divisor values is from 2 to 1025, and is equal to the programmed value of n plus 2.
ds1077 7 of 17 (refer to table 5) table 5 bit value divisor (n) 0 000 000 000 ** 2 0 000 000 001 3 -- -- -- -- 1 111 111 111 1025 **default condition bus word name ---bwca2a1a0 factory default0*0*0*0* 0 0 0 0 *these bits are reserved and must be set to ?0? zero a0,a1,a2 (default setting = 000) these are the device select bits which determine the address of the device. wc (default setting wc=0) this bit determines when/if the eeprom is written to after register contents have been changed. if wc = 0 the eeprom is written automatically after a write register command. if wc = 1 the eeprom is only written when the ?write ? command is issued. regardless of the value of the wc bit the value of the bus register (a0,a1,a2) is always written immediately to the eeprom. 2-wire serial data bus the ds1077 supports a bi-directional two-wire bus and data transmission protocol. a device that sends data onto the bus is defined as a transmitter, and a device receiving data as a receiver. the device that controls the message is called a "master". the devices that are controlled by the master are "slaves". the bus must be controlled by a master device which generates the serial clock (scl), controls the bus access, and generates the start and stop conditions. the ds1077 operates as a slave on the two-wire bus. connections to the bus are made via the open-drain i/o lines sda* and scl. a pullup resistor (5k) is connected to sda the following bus protocol has been defined (see figure 2): ? data transfer may be initiated only when the bus is not busy. ? during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as control signals.
ds1077 8 of 17 accordingly, the following bus conditions have been defined: bus not busy: both data and clock lines remain high. start data transfer: a change in the state of the data line, from high to low, while the clock is high, defines a start condition. stop data transfer: a change in the state of the data line, from low to high, while the clock line is high, defines the stop condition. data valid: the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. the number of data bytes transferred between start and stop conditions is not limited, and is determined by the master device. the information is transferred byte-wise and each receiver acknowledges with a ninth bit. within the bus specifications a regular mode (100khz clock rate) and a fast mode (400khz clock rate) are defined. the ds1077 works in both modes. acknowledge: each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. the master device must generate an extra clock pulse which is associated with this acknowledge bit. a device that acknowledges must pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. when the ds1077 eeprom is being written to, it will not be able to perform additional responses. in this case, the slave ds1077 will send a not acknowledge to any data transfer request made by the master. it will resume normal operation when the eeprom operation is complete. a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave must leave the data line high to enable the master to generate the stop condition.
ds1077 9 of 17 data transfer on 2-wire serial bus (figure 2) msb slave address r/w direction bit sda scl start condition 12 6789 12 89 stop condition or repeated start condition 3 - 8 acknowledgement signal from receiver acknowledgement signal from receiver ack ack repeated if more bytes are transferred figure 2 details how data transfer is accomplished on the two-wire bus. depending upon the state of the r/w* bit, two types of data transfer are possible: 1. data transfer from a master transmitter to a slave receiver. the first byte transmitted by the master is the slave address. next follows a number of data bytes. the slave returns an acknowledge bit after each received byte. 2. data transfer from a slave transmitter to a master receiver. the first byte (the slave address) is transmitted by the master. the slave then returns an acknowledge bit. next follows a number of data bytes transmitted by the slave to the master. the master returns an acknowledge bit after all received bytes other than the last byte. at the end of the last received byte, a 'not acknowledge' is returned. the master device generates all of the serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since a repeated start condition is also the beginning of the next serial transfer, the bus will not be released. the ds1077 may operate in the following two modes: 1. slave receiver mode: serial data and clock are received through sda and scl. after each byte is received, an acknowledge bit is transmitted. start and stop conditions are recognized as the beginning and end of a serial transfer. address recognition is performed by hardware after reception of the slave address and direction bit. 2. slave transmitter mode: the first byte is received and handled as in the slave receiver mode. however, in this mode, the direction bit will indicate that the transfer direction is reversed. serial data is transmitted on sda by the ds1077 while the serial clock is input on scl. start and stop conditions are recognized as the beginning and end of a serial transfer.
ds1077 10 of 17 slave address a control byte is the first byte received following the start condition from the master device. the control byte consists of a four bit control code; for the ds1077, this is set as 1011 binary for read and write operations. the next three bits of the control byte are the device select bits (a2, a1, a0) and can be written to the eeprom. they are used by the master device to select which of eight devices are to be accessed. the select bits are in effect the three least significant bits of the slave address. the last bit of the control byte (r/w*) defines the operation to be performed. when set to a one a read operation is selected, and when set to a zero a write operation is selected. following the start condition, the ds1077 monitors the sda bus checking the device type identifier being transmitted. upon receiving the 1011 code ( changeable with one mask) and appropriate device select bits, the slave device outputs an acknowledge signal on the sda line.
ds1077 11 of 17 2-wire serial communication with ds1077 figure 3 1 s 1 c0 0 01 wap sd a scl address byte command byte start ds1077 ack stop ds1077 ack send a ?standalone? command c1 c2 c3 c4 c5 c6 c7 a a2 a1 a0 write msb of a two-byte register 1 s c0 0 wa sd a scl address byte command byte start ds1077 ack ds1077 ack c1 c2 c3 c4 c5 c6 c7 a d0 ap msbyte stop ds1077 ack d1 d2 d3 d4 d5 d6 d7 1 s c0 0 wa sd a scl address byte command byte start ds1077 ack ds1077 ack write to a two-byte register c1 c2 c3 c4 c5 c6 c7 a d0 msbyte d1 d2 d3 d4 d5 d6 d7 a ds1077 ack d0 ap lsbyte stop ds1077 ack d1 d2 d3 d4 d5 d6 d7 1 s c0 0 wa sd a scl control byte command byte start ds1077 ack ds1077 ack write a single byte to an addressed register c1 c2 c3 c4 c5 c6 c7 a a0 byte address a1 a2 a3 a4 a5 a6 a7 a ds1077 ack d0 ap data byte stop ds1077 ack d1 d2 d3 d4 d5 d6 d7 byte (n+1) d1 d2 d3 d4 d5 d6 sd a scl d7 byte n d1 d2 d3 d4 d5 d6 d7 d0 a ds1077 ack d0 ap stop ds1077 ack 1 s c0 0 wa sd a scl control byte command byte start ds1077 ack ds1077 ack write multiple bytes to an addressed register c1 c2 c3 c4 c5 c6 c7 a a0 starting byte address a1 a2 a3 a4 a5 a6 a7 a ds1077 ack d0 a byte n ds1077 ack d1 d2 d3 d4 d5 d6 d7 1 01 a2 a1 a0 1 01 a2 a1 a0 1 01 a2 a1 a0 1 01 a2 a1 a0
ds1077 12 of 17 2-wire serial communication with ds1077 figure 3 (con?t) 1 s 1 c0 01 w sda scl control byte command byte start ds1077 a ck read single byte register or msb from a two-byte register c1 c2 c3 c4 c5 c6 c7 a 1 r 01 rd a control byte repeated start ds1077 a ck a ds1077 a ck np msbyte stop master nack d1 d2 d3 d4 d5 d6 d0 d7 a 2 a 1 a 0 1 a 2 a 1 a 0 np lsbyte stop master nack d1 d2 d3 d4 d5 d6 d0 sda scl d7 1 s c0 01 w sda scl control byte command byte start ds1077 a ck read from a two-byte register c1 c2 c3 c4 c5 c6 c7 a 1 r 01 a control byte repeated start ds1077 a ck a ds1077 a ck a msbyte master a ck d1 d2 d3 d4 d5 d6 d7 d0 1 a 2 a 1 a 0 rd 1 a 2 a 1 a 0 1 s 1 c0 01 w sda scl control byte command byte start ds1077 a ck read multiple bytes from an addressed register c1 c2 c3 c4 c5 c6 c7 a a ds1077 a ck a 2 a 1 a 0 1 r 01 rd a control byte repeated start ds1077 a ck a 1 a 2 a 1 a 0 a 0 starting byte address a 1 a 2 a 3 a 4 a 5 a 6 a 7 a ds1077 a ck np byte n stop master nack d1 d2 d3 d4 d5 d6 d0 d7 byte n d1 d2 d3 d4 d5 d6 sda scl d7 d0 a master a ck byte (n+1) d1 d2 d3 d4 d5 d6 d7 d0 a master a ck
ds1077 13 of 17 command set data and control information is read from and written to theds1077 in the format shown in figure 3 to write to the ds1077, the master will issue the slave address of the ds1077 and the r/w bit will be set to 0. after receiving an acknowledge, the bus master provides a command protocol. after receiving this protocol, the ds1077 will issue an acknowledge, and then the master may send data to the ds1077. if the ds1077 is to be read, the master must send the command protocol as before, and then issue a repeat start condition and then the control byte again, this time with the r/w bit set to 1 to allow reading of the data from the ds1077. the command set for the ds1077 is as follows: access div [01] if r/w is 0, this command writes to the div register. after issuing this command, the next data byte value is to be written into the div register. if r/w* is 1, the next data byte read is the value stored in the div register. access mux [02] if r/w is 0, this command writes to the mux register. after issuing this command, the next data byte value is to be written into the mux register. if r/w* is 1, the next data byte read is the value stored in the mux register. access bus [0d] if r/w is 0, this command writes to the bus register. after issuing this command, the next data byte value is to be written into the bus register. if r/w* is 1, the next data byte read is the value stored in the bus register. write e2 [3f] if wc=0 the eeprom is automatically written to at the end of each command, this is a default condition. in this case the command ?write e2? is not needed if wc=1, the eeprom is only written when the ?write e2? command is issued. on receipt of the ?write e2? command the contents of the div and mux registers are written into the eeprom, thus locking in the register settings. exception: the bus register is always automatically written to eeprom after a write, regardless of the value of wc
ds1077 14 of 17 absolute maximum ratings voltage on any pin relative to ground -1.0v to 6.0v operating temperature 0c to 70c storage temperature -55c to 125c soldering temperature see j-std-020a specifications dc electrical characteristics (t a = 0c to 70c, v cc = 5v+/-5%) parameter symbol condition min typ max units notes supply voltage vcc 4.75 5 5.25 v 1 high-level output voltage (out1,out0) v o h i oh = -4ma, v cc = min 2.4 v low-level output voltage (out1,out0) v o l i o l = 4ma, 0.4 v high-level input voltage (ctrl1,ctrl0,sda,s dl) v i h 2 v cc + 0.5v v low-level input voltage (ctrl1,ctrl0,sda,s dl) v i l v cc - 0.5v 0.8 v high-level input current (ctrl1,ctrl0,sda,s dl) i i h v ih = v cc =5.25v 1 ua low-level input current (ctrl1,ctrl0,sda,s dl) i i l v cc = 5.25v, v i l =0 -1 ua supply current (active) ds1077-133 ds1077-125 ds1077-120 ds1077-100 ds1077-66 i cc c l = 15pf (both outputs) 35 50 ma standby current (power-down) i ccq power-down mode 25 ua
ds1077 15 of 17 ac electrical characteristics (ta = 0c to 70c, vcc = 5v+/-5%) parameter symbol condition min typ max units notes output frequency tolerance ? f o v cc = 5v, t a = 25c -0.5 0 +0.5 % combined freq. variation ? f o over temp & voltage -1 +1 % output frequency min output frequency max f out 8.05 133 khz mhz 2 power up time t por + t stab 0.1 1 ms 5 enable out1 from pdn t stab 0.1 1 ms 3 enable out0 from pdn t stab 0.1 1 ms 3 out1 hi-z from pdn t stab 1ms 3 out0 hi-z from pdn t stab 1ms 3 load capacitance c l 15 50 pf 4 output duty cycle (out1,out0) 40 60 %
ds1077 16 of 17 ac electrical characteristics: 2-wire interface (0 c to +70 c, 4.5v v dd 5.25v) parameter symbol condition min typ max units notes scl clock frequency f scl fast mode 400 khz standard mode 100 bus free time between t buf fast mode 1.3 s a stop and start condition standard mode 4.7 hold time (repeated) t hd : sta fast mode 0.6 s 6 start condition. standard mode 4.0 low period of scl t low fast mode 1.3 s standard mode 4.7 high period of scl t high fast mode 0.6 s standard mode 4.0 set-up time for a t su : sta fast mode 0.6 s repeated start standard mode 4.7 data hold time t hd : dat fast mode 0 0.9 s 7,8 standard mode 0 data set-up time t su : dat fast mode 100 ns standard mode 250 rise time of both sda t r fast mode 20+ 0.1c b 300 ns 9 and scl signals standard mode 1000 fall time of both sda t f fast mode 20+ 0.1c b 300 ns 9 and scl signals standard mode set-up time for stop t su : sto fast mode 0.6 s standard mode 4.0 capacitive load for each bus line c b 400 pf 9 input capacitance c i 5pf notes: 1. all voltages are referenced to ground. 2. 8.05khz is obtained from a ?66mhz std part 3. pdn is a power down signal applied to either ctrl0 or ctrl1 pins as appropriate 4. output voltage swings may be impaired at high frequencies combined with high output loading 5. after this period, the first clock pulse is generated. 6. a device must internally provide a hold time of at least 300ns for the sda signal (referred to the v ih min of the scl signal) in order to bridge the undefined region of the falling edge of scl. 7. the maximum t hd : dat has only to be met if the device does not stretch the low period (t low ) of the scl signal.
ds1077 17 of 17 8. a fast mode device can be used in a standard mode system, but the requirement t su : dat >250ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t r max +t su : dat = 1000+250 = 1250ns before the scl line is released. 9. c b - total capacitance of one bus line in pf. timing diagram su:sto t t sp hd:sta t t su:sta su:dat t t high r t t low t hd:sta scl start sda stop t buf t f repeated start t hd:dat ordering information example: ds1077z-100 ds1077 z= soic u= usop 133 = 133.333 mhz 125 = 125.000 mhz 120 = 120.000 mhz 100 = 100.000 mhz 66 = 66.666 mhz

▲Up To Search▲

Price & Availability of DS1077Z-120

	To Download DS1077Z-120 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .